CozyDev

Stay curious

Security DMP

What are the key aspects?

DMP (Design for Manufacturing and Testability) techniques and methodologies aimed at enhancing the testability and manufacturability of integrated circuits. Security DMP Incorporates security considerations into the design process to ensure that the manufactured chips are resistant to various forms of attacks and unauthorized access. Key aspects of security DMP: Secure Test Access Mechanisms Ensures only authorized entities can access the test features of the chip. Secure mechanisms invoke: Implementing authentication Encryption mechanisms Tamper Resistance Protect against physical attacks: probing or tampering with the chip during testing or operation.

Posted by Eirik on Monday, April 15, 2024

Power Optimization Techniques

Tricks across frontend to backend

Techniques to optimize design power Clock tree optimization and clock gating Portions of the clock tree(s) that aren’t being used at any particular time are disabled. Operand isolation Reduce power dissipation in datapath blocks controlled by an enable signal; when the datapath element is not active, prevent it from switching. Logic restructuring Move high switching operations up in the logic cone, and low switching operations back in the logic cone; a gate-level dynamic power optimization technique.

Posted by Eirik on Tuesday, April 2, 2024

DFT Basics

Wafer level testing (Wafer Sort) Burn_in Testing (elevate voltage and temperature) x-axis (clock period) y-axis (Vdd) Final test(pass/fail) and Bin Sorting Parametric Tests(voltage, temperature and clock) Shmoo plot Wafer Sort | probe test Testing on the wafer (before diced) Check open/short on the pads Measure gate threshold, ploy sheet resistence,…etc Testing with probe cards cost 50~100k dollar depends on the yield and the cost of the packaging (economic problem) DC

Posted by Eirik on Tuesday, March 26, 2024

IEEE P1687 IJTAG

What are the differences

ICL ICL 檔案代表 Instrument Connectivity Language，用於描述測試儀器與待測晶片之間的連接資訊。 測試儀器的類型和配置 待測晶片的測試引腳 測試儀器與待測晶片之間的連

Posted by Eirik on Saturday, March 23, 2024

Verification | Testing

What are the differences

Verification Testing Verifies correctness of the design Verifies correctness of manufactured hardware Performed by simulation, hardware emulation or formal methods Test generation and test application Performed once prior to manufacturing Test application performed on every manufactured device Reponsible for quality of the design Responsible for quality of devices

Posted by Eirik on Saturday, March 23, 2024

FIR forms: direct | transpose

一種常用的濾波器，其結構可分為direct和transpose

面積 在面積方面，direct form的結構比較簡單，只需要一個乘法器和一個加法器，因此面積比較小。而transpose form的結構比較複雜

Posted by Eirik on Saturday, March 16, 2024

OCV | AOCV | POCV | LVF

What are the differences

OCV（On-Chip Variation）： OCV 是指在晶片上的元件之間存在的製造變異。這種變異可能來自於製造過程中的不確定性，例如晶圓製造、成

Posted by Eirik on Monday, March 11, 2024

SVE | SME

What are the differences

SVE SVE，或可擴充向量擴充（Scalable Vector Extensions），是一種新的指令集架構，專為向量處理設計。向量處理是一種並行處理，可用於

Posted by Eirik on Friday, March 8, 2024

Clock Tree Synthesis

Different clock-tree synthesis architecture

CTS（Clock Tree Synthesis）、Multisource CTS 和時鐘網格（Clock Mesh）是在Digital IC design中用於時鐘

Posted by Eirik on Tuesday, March 5, 2024

xPU

CPU model and performance Naming cenvention Intel AMD Example Core-i7-10875H Ryzen 7-5800H Series Core-i7 Ryzen 7 Generation 10 5 Performance 875 800 Product line H H Series 對比 Level Intel AMD 入門 Pentium Athlon 低階 Core-i3 Ryzen 3 中階 Core-i5 Ryzen 5 高階 Core-i7 Ryzen 7 旗艦 Core-i9 Ryzen 9 Product line 對比 CPU Benchmark Product line Intel AMD 超低功耗

Posted by Eirik on Tuesday, March 5, 2024

avatar

Hardware Engineer, Coder and Life Adventurer

Quick Links
Tags