DFT

DFT Basics

Posted by Eirik on 26 Mar, 2024

Wafer level testing (Wafer Sort)

Burn_in Testing (elevate voltage and temperature) x-axis (clock period) y-axis (Vdd) Final test(pass/fail) and Bin Sorting

Parametric Tests(voltage, temperature and clock)

  • Shmoo plot

Wafer Sort | probe test

  • Testing on the wafer (before diced)
  • Check open/short on the pads
  • Measure gate threshold, ploy sheet resistence,…etc

Testing with probe cards

cost 50~100k dollar depends on the yield and the cost of the packaging (economic problem)

DC electrical Tests

  • DC contact tests - Calculate pin res
  • Power consumpsion test - Measure max current at worst case temperature
  • Output short circuit test - Measure current driven when output is short
  • Output drive current test - Measure current for 1 and 0 outputs
  • Threshold tests - Measure VIH and VIL of input pads

AC Parametric Tests

  • Rise/Fall time tests
  • Setup/Hold time tests
  • Propagation delay tests

Brun-in Test | Stress Test

Put chips in the oven

  • Subject chips to high temperature and over-voltage supply, while running production tests.
  • Long simulation time with high temperature (simulation years of aging)
  • Plot in bathtub curve
  • Target catches: Find out infant mortality (weak connection)

Die Cost

  • Wafer Cost / Dies per Wafer * Die Yield (#Good dies)
  • IC Cost = Die Cost + Testing Cost + Packaging Cost / Final Test Yield

Defect Level (DL)

  • The ratio of faulty chips among the chips that pass tests, measured in DPM («500DPM)
  • DL = 1-Y^(1-FC) , 0< DL < 1-Y

Testing Processes

  • Fault Modeling
  • Test Generation
  • Fault Simulation
    • Given a circuit, a set of faults F, and a set of test vectors T, determines the faults in F are tested by the vectors in T.

Terminologies

Defects Faults Errors
Physical phenomenon Abstract representation Operational results
  • Different types of defects can cause same fault.

Common Fault Models

  • Stuck-At Fault (s/0, s/1)
  • Transition/Delay Faults ()
  • Other fault models(open/short/bridging)

Concurrent Fault Simulation

用現在test pattern 在每一個gate會產生的golden output當作reference 對每個gate 做fault:input:output的列表forward propagate 就可以知道當前的pattern可以detect到的fault list 進而得知fault coverage

Test Genreration

D-algorithm

把faulty site 記為D ，直到propagate 到observation point or PPO 為止， 再做backtracking 找出必要assign 的PPI 和assign value (也可能是don’t care bit X)

Test generation is slower than test simulation!

Design For Test

Because circuit PI/PO are limited, it’s hard to control the states through ultiple pipelines

  • Ad hoc
  • Scan Chains
    • Scan-In
    • Scan-Out
    • Scan Enable
  • Built-in Self Test (BIST)

Shorter scan chain Scan clock is usually slow (100-200MHz) Usually implement parallel scan

Special care needs to be taken to avoid undesirable conditions during scan, e.g, bus contentions, resets, clock gates One ther problem is excessive current draw due to many flops toggling at the same clock

How AC testing switch from slow sfift clock to on-chip clock and switch it back in accuracte number of clock cycles ?

IDDQ Test

Test the quiescent power consumption

Pros:

  • Covers non-stuck-at faults
  • Cheap test equipments
  • Few test patterns

Cons:

  • Slow current measurment
  • Difficult to measure proper IDDQ threshold
  • Not practicable for sub-micron processes

Build-in Self Test

Since ATE is expensive Especially for memories

  • BIST Enable
  • Test control logic will output pass|fail
  • Can run at-speed

BIST Architecture

  • Controller Counter
  • TG(Test Generator)
  • ORA(Output Response Analyzer)
  • Golden Value Storage ROM

LFSR(Linear Feedback Shift Register)

  • Pseudo-Random Pattern Generator
  • Patterns depends on :
    • Feedback function (XOR, XNOR)
    • Tap Selection
    • Seed(initial value)
  • Properties
    • Tap described by characteristic polynomial
    • Primitive Polynomials cannot be factored
    • Cannot initialize all 0 or all 1

Response Compaction

  • A response compactor (not compressor) reduce the response into a signature (hashing) before final bist comparison
  • The golden signature is stored on-chip
    • Similar to cyclic redundency check(CRC)
  • This is basically a many-to-one mapping
    • Can cause alias(low probability)
  • 2 approaches
    • Signature Analyzer
      • Compact a serial bit stream into an LFSR based compator
    • Multiple-input Signature Register(MISR)
      • compact several bit streams in parallel

MBIST

  • Implements commonly used testing algorithm
    • Zero-One
    • Checkboard
    • GALPAT
    • Walking 1/0
    • March (Most popular)

BISR(Build-in Self Repair)

  • In memory
  • To avoid yield loss redundant or spare rows and column are added
  • Memory repair swaps out faulty rows|colums for spare ones

LBIST(Logic Built-in Self Test)

IEEE1149.1 Boundary scan (JTAG)

  • How about board testing?

    • Need to verify solder joints are good
    • Drive pin to 0 -> 1
    • Check all connected pins gets the value

  • Through-hold boards used bed of nails

  • SMT and BGA boards connot easily contact pins

  • JTAG(Joint Test Action Group) Standard

    • Build capability to observing and controlling pins into each chip to make board test easier

  • Used for board (PCB) level testing

  • Implementation

    • TAP controller (Test Access Point)
    • 4 dedicated IO pins
      • TCK test clock
      • TMS test mode select
      • TDI test data in
      • TDO test data out
      • TRST test reset (optional)
    • Allows to drive and sample the device IO pins
    • Implementation is described in BSDL(Boundary Scan Description Language)

1149.1 Wrapper

  • TDRs
  • Important Test Modes
    • EXTEST
      • Test the interconnection betweens devices|chips.
    • BYPASS
      • Forword test to next devices|chips.
    • INTEST
      • Test the internal logic of a devices|chips.

Test Engineer Requirements

  • hardware design requirements (CPM/IBIS models, SI/PI simulation) for probe-card, load-board, burn-in boards

  • ATE test equipment (Advantest SMT8 preferred) writing Scan/Mbist/PHY tests

  • Advantest 93K, Teradyne Uflex

  • developing product binning test methods

  • HVM shipment of Silicon

DFT mbif

一種用於描述記憶體建置中建置內建自檢 (BIST) 的資訊檔案。它是一種 XML 格式的檔案，其中包含有關記憶體陣列及其測試的詳細資訊。

DFT mbif 檔案目的：

  • 在 EDA 工具之間共享記憶體 BIST 資訊
  • 生成記憶體 BIST 模式
  • 分析記憶體 BIST 結果

DFT mbif 檔案中資訊：

  • 記憶體陣列的物理佈局
    • 記憶體陣列的物理佈局描述了記憶體單元在晶片上的位置。此資訊對於生成記憶體 BIST 模式很重要，因為它允許測試工具確定如何訪問每個記憶體單元。
  • 記憶體 BIST 模式
    • 記憶體 BIST 模式是一系列用於測試記憶體陣列的指令。這些模式旨在檢測記憶體陣列中的任何故障。
  • 測試結果
    • 測試結果表明記憶體 BIST 是否成功。此資訊對於分析記憶體陣列的可靠性很重要。
  • 記憶體陣列的物理佈局

DFT mbif 檔案對於設計用於複雜晶片的工具很重要。它們允許這些工具共享有關記憶體 BIST 的資訊，並生成有效且高效的測試模式。

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