Power Optimization Techniques
Tricks across frontend to backend
Techniques to optimize design power Clock tree optimization and clock gating Portions of the clock tree(s) that aren’t being used at any particular time are disabled. Operand isolation Reduce power dissipation in datapath blocks controlled by an enable signal; when the datapath element is not active, prevent it from switching.
Logic restructuring Move high switching operations up in the logic cone, and low switching operations back in the logic cone; a gate-level dynamic power optimization technique.
Posted by Eirik on Tuesday, April 2, 2024
